1. Technical Field
This invention relates to multi-layer superconductive substrates and, more particularly, to fabricating multi-layered superconductive interconnects for superconductive multi-chip modules, printed circuit boards and other applications.
2. Discussion
Multi-chip modules typically include multiple integrated circuits mounted on a printed-circuit board. Each integrated circuit is typically connected to one or more of the other integrated circuits on the printed-circuit board, and, thus, interconnections or interconnects between the integrated circuits are required. The number of interconnect layers required depends upon the number of integrated circuits and connections therebetween.
Conventional nonsuperconductive interconnects have several performance drawbacks when used in electronic circuits such as multi-chip modules. For example, their direct current (DC) resistance and alternating current (AC) losses tend to increase the power required to operate the electronic circuits. Their relatively low current carrying capacity increases the number of interconnect lines or layers required to carry a given current than would be required for interconnects with higher current carrying capacities. Due to their DC resistance characteristics, conventional nonsuperconductive interconnects also experience electron migration which degrades interconnect lines, reduces current carrying capacity and eventually may cause open circuits.
Conventional superconductive interconnects alleviate most of the drawbacks of the nonsuperconductive interconnects. Conventional superconductive interconnects have no DC resistance and low AC loss. Conventional superconductive interconnect lines carry higher current than conventional nonsuperconductive (or metal) lines having the same physical dimensions at both room temperature and at cryogenic operating ambient temperatures. Conventional superconductive interconnects also have lower power consumption and electron migration problems. As a result of increased current carrying capacity, superconductive multi-layered interconnects have increased durability and employ fewer interconnect layers than conventional nonsuperconductive interconnects.
While the use of superconducting multi-layer interconnects is desirable, conventional methods of fabricating superconducting interconnects have several drawbacks. Fabrication of conventional superconductive multi-layered interconnects typically involves a standard integrated circuit (IC) process approach in which a first superconducting layer is deposited on a substrate. A dielectric layer is then deposited on the first superconducting layer. Via contacts are patterned if required. A second superconducting layer is thereafter deposited and patterned on the dielectric layer. This process is repeated to increase interconnect layers if required. Additional interconnect layers may be required depending upon the number of integrated circuits and required connections therebetween.
Significant problems are associated with the conventional methods of fabricating superconductive multi-layered interconnects. Forming a crystalline layer over nonplanar surfaces (often referred to as "steps") is far more difficult than forming a crystalline layer on a planar surface. Therefore, it is difficult to deposit an epitaxial dielectric layer with a low dielectric constant on a first superconducting layer which includes steps. The nonplanarity of the step disrupts grain growth. Current density is significantly reduced for superconducting layers crossing over nonplanar steps primarily due to grain boundaries. Still other problems include the tendency of the second superconducting layer to fill pinholes in the first dielectric layer which can cause a short circuit between the first and second superconducting layers.
Conventional superconductive multi-layered interconnects become even more nonplanar as additional interconnect layers are added. As a result, it becomes even more difficult to deposit high quality superconducting layers on the underlying dielectric layer.
Therefore, a superconductive interconnect having dielectric layers with a low dielectric constant, high quality/yield superconducting layers with high current density, and a maximum number of planar layers is desirable.